Over the last few decades, the electronics industry has continually driven toward higher performance and functionality in smaller form factors. At the production level, these driving forces have translated into smaller circuit features, designs and manufacturing methods that support more efficient circuit routing, elimination of packaging layers and sophisticated engineered materials. However, progress has come at the cost: close juxtaposition of dissimilar materials has made it more difficult to manage thermo-mechanical stresses management and thermal transfer.
One trend in the design of printed circuit boards and semiconductor packaging has been to shift from a through-hole vertical interconnection architecture to a direct layer-to-layer interconnection architecture to optimize circuit routing for speed and performance. Ideally the conductive vias that interconnect layers of circuitry would be commensurate in size with the circuit traces that they interconnect, provide rugged and reliable conduction, require very small connecting circuit features, and could be stacked or otherwise placed freely anywhere in a circuit board or package design. It is cost prohibitive to plate solid metal vias to form such layer-to-layer interconnections and entrapment of plating solution is a significant issue. Instead, the topography of a via hole is frequently plated to a reasonable thickness. However, this strategy creates mechanical stress points at the edge of the via and at the point where plating connects with an underlying pad. The dimple created in the center of the via can also be a source of defects. Although via holes can be filled with conductive compounds, such via fill materials do not form electrically robust interfaces with copper pads.
In addition to miniaturization, there is an emerging trend toward integrating electronic devices or elements thereof directly into other objects. Full realization of this trend will require 3-D architectures and suitable manufacturing methods. Innovative interconnection strategies will be required for applications as diverse as interconnecting the I/Os of stacked semiconductor die, creating conformable or embedded antenna structures for wireless devices and creating collection grids on solar panels.
Increasingly, this trend has led to applications where dissimilar materials must be adhered together. Examples include attachment of components to circuit boards, and attachment of integrated circuits (ICs) to lead frames, redistribution layers and heat sinks. In many applications, thermal conduction between the adherands is at least as important as electrical conduction. The critical elements for a successful adhesive are the quality of the adhesive bond; the bulk electrical and thermal conductivity of the adhesive; the thermal, mechanical and electrical quality of the interfaces between the adhesive and the adherands; and the ability of the adhesive to mitigate differences in coefficient of thermal expansion of the adherands. Solder is often used to attach components to circuit boards, to adhere heat sinks to components, and to attach ICs to packages. Soldering a component to a heat sink or board/package generally requires high temperatures, and the surfaces to be joined must be wettable by the soldering material for adhesion to occur. In addition, the intermetallic and alloy phases of a soldered joint are not well matched to the coefficient of thermal expansion of the materials to be thermally connected, which results in high thermal mismatch stress. Repeated thermal cycling can cause microstructural coarsening, resulting in creep rupture. Gold-silicon and gold-tin are both gold-rich eutectic compositions that are used in high power semiconductor applications where conventional solders and adhesives do not have sufficient thermal conductivity. The major drawback for both of these materials is their very high cost. Also, compared to other lower temperature solders, both AuSn and AuSi have low ductility making CTE stress an issue, particularly at high die attach temperatures. The primary benefit of using solder as an electronic adhesive is the alloyed interfaces and high bulk thermal conductivity. The main detriments are the stress on the die from CTE mismatch and the complications for subsequent assembly operations.
Polymeric adhesives are a common alternative to solder because their mechanical characteristics can be tailored and because they do not require solderable adherands. The thermal conductivity (k) of pure polymer adhesives is generally poor (typically 0.2 to 0.3 W/m° K) and most polymer materials are electrical insulators. To increase the thermal and electrical conductivity of polymer adhesives, conductive filler particles can be added to an adhesive formulation. The primary advantage of thermally and electrically conductive adhesive compositions is that they are easily applied and processed resulting in nearly 100% coverage of the interface. The primary disadvantages are that the electrical/thermal interfaces as well as the bulk electrical/thermal conductivity are dependent upon particle-to-particle contact. At percolation threshold, an average of 1.5 contacts per particle is typical and these contacts are vulnerable to environmental degradation.
A further trend is the reduction and eventual elimination of environmental hazards and toxins, including volatile organic compounds and lead. The elimination of once ubiquitous lead, in particular has complicated electronic device manufacture. The industry has coalesced around high tin alloys as a replacement for tin-lead. High tin alloys have melting temperatures roughly 30° C. higher than the tin-lead alloys that they replace, resulting in commensurate increases in component assembly process temperatures, which can increase thermo-mechanical stresses on increasingly fine-featured electrical interconnects.
As semiconductor packaging and printed circuit board production converge, substantial engineering effort has been devoted to creating materials than can withstand the rigors of the new architectures and processing regimes. For example, the microstructure of copper foil used to produce the fine circuits has become highly controlled. Composite laminates that are used to create circuit substrates have undergone extensive product development to control flow characteristics, glass transition temperature, coefficient of thermal expansion, and high quality hole formation. Surface preparation chemistries and primer coatings have also been extensively characterized and optimized. Barrier metals and surface finishes are now applied to strict tolerances; dopants are now added to the mechanical characteristics of solder joints and prevent undesirable microstructures such as tin whiskers from forming.
Despite these measures, there remains a need for inexpensive, robust, low process temperature and reliable electrical and thermal interconnection strategies for critical junctions within electronic devices.
TLPS
Transient liquid phase sintering (TLPS) materials were introduced nearly two decades ago as a reliable and versatile conductive paste solution to printed circuit board interconnection challenges. Primarily lead-based alloys were blended with copper particles in a fluxing binder. The compositions could be processed like conventional lead-tin solders and formed robust metallurgical junctions to solder wettable surfaces. Unlike solder, however, TLPS compositions created a metal “thermoset” during processing, such that TLPS paste materials could be used on or in circuit boards, and in operations where step soldering was typically required, and the processed composition would not remelt at the original process temperature.
The requirements for these early TLPS materials were that they metallurgically react to form a electrically conductive interconnections, remain solid through subsequent thermal processing, self-inert, and provide a reasonably solderable surface. The microstructure of the metal network formed and the surrounding organic matrix were optimized only to the extent that characteristics such electrical conductivity and adhesion were improved. The size of the interconnections was relatively large and the processed TLPS materials were rarely subjected to subsequent thermal excursions in excess of 220° C.
Early TLPS materials relied heavily on lead due to its low process temperature, excellent wetting of copper, reasonably good electrical and thermal conductivity, and ductile, predominantly lead, bridges between copper-tin intermetallic sheathed copper particles in the cured TLPS composition. The elimination of lead presented significant challenges to realizing the potential of TLPS technology.
TLPS compositions have been used as replacements for conventional electrically and/or thermally conductive materials in a wide variety of applications including assembly of electronic components, in-plane circuit traces, interconnection of circuit traces on different planes, assembly of unpackaged integrated circuit die onto packaging elements, and the like. See U.S. Pat. Nos. 6,716,036; 5,980,785; 5,948,533; 5,922,397; 5,853,622; 5,716,663 and 5,830,389, the contents of which are incorporated herein by reference in their entireties.
To meet the increasing demands of modern electronic packaging, TLPS interconnect materials must be carefully engineered as application-specific composites. Desired properties in TLPS materials include those listed in Table 1.
TABLE 1Desirable Properties of TLPS MaterialsForm interconnected metallurgical networksProcessing at temperatures below 250° C.High specificity of metallurgical component selectionHigh tolerance to thermo-mechanical stressThermally stable bulk and interfacial electrical and thermal resistancePreferably lead-freeInclude an interpenetrating organic network that is applicationspecific to the adherands and surrounding materials
In addition, TLPS pastes can be useful as adhesives in the electronics industry. By incorporating traditional polymer-based adhesive components with a reactive metallurgy, a thermosetting polymer network can be formed that interpenetrates and reinforces the TLPS metallic network. During TLPS processing of the typical particles of elemental copper and tin alloy at process temperature typically below 200° C., the alloy particles melt and essentially “microsolder” the copper particles into a network structure. When TLPS material is in contact with solderable surfaces, these surfaces are also wet by the alloy powder to create alloyed interfaces. Unlike the laminar interface that solder materials form, the interface between the TLPS material and the solderable surface is composed of a matrix of organic adhesive and microsolder joints.
While this technology is promising for electronic adhesive applications, it does suffer from some serious limitations. The bismuth typically used to create a low-process-temperature alloy is an extremely poor thermal conductor and is brittle. Consequently, the intermetallics formed during the creation of the metallic network are brittle and poorer conductors than the core metals used. Unfortunately the metallic matrix formed with TLPS tends to dominate the mechanical characteristics of the processed adhesive, thereby limiting the ability to tailor the organic matrix to mitigate the CTE mismatch stress.
Therefore, there exists a need in the field of electronic adhesives for improved adhesive material that simultaneously provides high bulk thermal and electrical conductivity, low and stable interfacial thermal and electrical resistance, high adhesive strength, and the ability to mitigate stress caused by differences in coefficient of thermal expansion of the adherands.